The present invention relates to a series regulator circuit that suppresses current consumption.
In the prior art, a series regulator circuit is known as a circuit that outputs a constant voltage even if the input voltage changes. Proposals have been made for a series regulator circuit to improve response with low current consumption (refer to, for example, FIG. 1 of Japanese Laid-Open Patent Publication No. 2004-62374, and FIG. 1 of Japanese Laid-Open Patent Publication No. 2002-343874).
The series regulator circuit described in Japanese Laid-Open Patent Publication No. 2004-62374 includes an error amplification circuit incorporates a two-stage amplification circuit, which include a differential amplification circuit and a source-ground amplification circuit, and a phase compensation circuit, which includes a resistor and a capacitor. Output is amplified by a further source-ground amplification circuit. Therefore, the series regulator circuit, which ultimately is a three-stage voltage amplification circuit, enables the GB product to be increased with a relatively low current consumption and improves response. Furthermore, the phase compensation circuit, which includes the resistor and the capacitor, compensates for phase delays in the series regulator circuit so as to avoid the demerit of the three-stage voltage amplification circuit, which is a phase delay of 180° or greater.
In the series regulator circuit described in Japanese Laid-Open Patent Publication No. 2002-343874, the output of a differential amplifier is input to the gate terminal of a transistor, which forms a source-ground amplification circuit, and further amplified by a source-ground circuit, which includes an output transistor and a load. The series regulator circuit ultimately has a three-stage voltage amplification circuit. Thus, the GB product can be increased with relatively low current consumption, and the response may be increased. Phase delays of 180° or greater is also avoided by the series regulator circuit described in Japanese Laid-Open Patent Publication No. 2002-343874 by using a resistor and capacitor in the circuit.
However, the series regulator circuits described in Japanese Laid-Open Patent Publication No. 2004-62374 and Japanese Laid-Open Patent Publication No. 2002-343874 are three-stage voltage amplification circuits. Thus, current is consumed by each voltage amplification circuit. Accordingly, proposals have been made to further reduce current consumption with a two-stage voltage amplification circuit (refer to, for example, FIG. 1 of Japanese Laid-Open Patent Publication No. 9-265330).
Japanese Laid-Open Patent Publication No. 9-265330 describes a reference potential generation circuit, which uses a series regulator formed by a two-stage voltage amplification circuit. The series regulator will now be described with reference to FIG. 5. The series regulator circuit 50 includes a constant current source IP, which is connected to an input voltage VIN line, and a bipolar transistor B1, which has a collector terminal connected to the constant current source IP. The emitter terminal of the transistor B1 is connected to a ground voltage GND line by via a resistor element 51 having resistance R1.
The series regulator circuit 50 includes an n-channel MOS transistor 61. The drain terminal of the MOS transistor 61 is connected to the input voltage VIN line. The source terminal of the MOS transistor 61 is connected to the ground voltage GND line via resistor elements 52 and 53 of resistances R2 and R3. The voltage VOUT at the source terminal of the MOS transistor 61 is the output voltage of the series regulator circuit 50. Furthermore, the gate terminal of the MOS transistor 61 is connected to a connection node of the constant current source IP and the collector terminal of the transistor B1. The connection node of the resistor elements 52 and 53 is connected to the base terminal of the transistor B1.
The voltage VOUT at the output terminal of the series regulator circuit 50 may fluctuate in accordance with the load current. When the load current increases and the output voltage decreases, the base voltage VBG at the base terminal of the transistor B1 decreases. This accordingly lowers the collector current. In this case, the voltage at the collector terminal side, that is, the voltage vg1 at the gate terminal of the MOS transistor 61 increases. This decreases the resistance value between the drain and the source of the MOS transistor 61 and increases the voltage VOUT. Therefore, the series regulator circuit 50 keeps the voltage VOUT at the output terminal constant through feedback based on the base voltage VBG of the transistor B1.
The stability of the series regulator circuit 50 will now be described. FIG. 5 shows a case in which the base voltage VBG line of the series regulator circuit 50 is cut. Specifically, input signal voltage vbgi is supplied to the base voltage VBG line. The influence on the stability of an output signal voltage vbgo at the base voltage VBG line will be discussed for this case.
Furthermore, an equivalent circuit shown in FIG. 6 will be used to discuss the characteristics of this circuit. In the equivalent circuit of FIG. 6, a synthesized conductance of the transistor B1 and the resistor element 51 is represented by gm1. The synthesized resistance of the series regulator circuit 50 is represented by Rg1. Specifically, the synthesized resistor Rg1 includes the resistance between the collector and emitter of the transistor B1, the resistance of the constant current source IP, the resistance R1 of the resistor element 51, and wiring resistance. The capacity Cg1 of the series regulator circuit 50 represents synthesized capacitance of the series regulator circuit 50. The capacitance Cg1 includes wiring capacitance, capacitance of the constant current source IP, and parasitic capacitance at the gates of the transistor B1 and the MOS transistor 61. The capacitance of the load Lo is represented by CL.
In this case, when the input signal voltage vbgi is input to the transistor B1, current (vbgi·gm1) is output. Thus, the current equation for the voltage vg1 line is vg1·s·Cg1+vg1/Rg1−vbgi·gm1=0 (s is a Laplace operator). Voltage vg1 is represented by the following equation (1).
                              vg          ⁢                                          ⁢          1                =                                            vbgi              ·              gm                        ⁢                                                  ⁢            1                                                              s                ·                Cg                            ⁢                                                          ⁢              1                        +                          1                              Rg                ⁢                                                                  ⁢                1                                                                        (        1        )            
When voltage vg1 is input to the MOS transistor 61, current (vg1−VOUT)·gm2) is output. Thus, the current equation for the output terminal is VOUT·s·CL+VOUT/(R2+R3)−(vg1−VOUT)·gm2=0. Voltage VOUT is represented by the following equation (2).
                    VOUT        =                              vg            ⁢                                                  ⁢                          1              ·              gm                        ⁢                                                  ⁢            2                                              gm              ⁢                                                          ⁢              2                        +                          s              ·              CL                        +                          1                                                R                  ⁢                                                                          ⁢                  2                                +                                  R                  ⁢                                                                          ⁢                  3                                                                                        (        2        )            
The voltage vg1 of equation (2) is substituted by equation (1) to obtain equation (3).
                    VOUT        =                                            vbgi              ·              gm                        ⁢                                                  ⁢                          1              ·              gm                        ⁢                                                  ⁢            2                                              (                                                                    s                    ·                    Cg                                    ⁢                                                                          ⁢                  1                                +                                  1                                      Rg                    ⁢                                                                                  ⁢                    1                                                              )                        ⁢                          (                                                gm                  ⁢                                                                          ⁢                  2                                +                                  s                  ·                  CL                                +                                  1                                                            R                      ⁢                                                                                          ⁢                      2                                        +                                          R                      ⁢                                                                                          ⁢                      3                                                                                  )                                                          (        3        )            
The output signal voltage vbgo is expressed by equation (4) from the voltage division by resistances R2 and R3.vbgo=VOUT·R3/(R2+R3)  (4)
The voltage VOUT of equation (4) is substituted by equation (3) to obtain the following equation (5).
                    vbgo        =                                            vbgi              ·              gm                        ⁢                                                  ⁢                          1              ·              gm                        ⁢                                                  ⁢                          2              ·              R                        ⁢                                                  ⁢            3                                              (                                                                    s                    ·                    Cg                                    ⁢                                                                          ⁢                  1                                +                                  1                                      Rg                    ⁢                                                                                  ⁢                    1                                                              )                        ·                          {                                                                    (                                                                  R                        ⁢                                                                                                  ⁢                        2                                            +                                              R                        ⁢                                                                                                  ⁢                        3                                                              )                                    ⁢                                      (                                                                  gm                        ⁢                                                                                                  ⁢                        2                                            +                                              s                        ·                        CL                                                              )                                                  +                1                            }                                                          (        5        )            
Accordingly, gain=output signal voltage/input signal voltage=vbgo/vbgi is satisfied, and equation (6) shown in FIG. 7 is obtained. The Bode diagram shown in FIG. 7 is based on equation (6). In the Bode diagram of FIG. 7, the gain-frequency approximate curve is shown at the upper side and the phase-frequency approximate curve is shown at the lower side. As apparent from equation (6), frequencies fc1 and fc2, which are line frequencies of the Bode diagram, are respectively expressed by equations (7) and (8).
If the capacitance CL of the load Lo is sufficiently larger than the capacitance Cg1, the frequency fc1 becomes lower than the frequency fc2. The frequency response of the series regulator circuit 50 is a second-order lag element as apparent from equation (6). Thus, phase delays of −45 degrees and −135 degrees respectively occur for frequencies fc1 and fc2 in FIG. 7. It can be understood from equation (7) that the frequency fc1 fluctuates in accordance with the capacitance CL of the load Lo. Furthermore, it can be understood from equation (8) that the frequency fc2 is irrelevant from the capacitance CL of the load Lo and always take a constant value. The gradient of the gain-frequency approximate curve changes at frequencies fc1 and fc2.
In FIG. 7, the approximate curve when the capacitance CL of the load Lo is large is shown by a solid line, and the approximate curve when the capacitance CL of the load Lo is small is shown by a broken line. Since the frequency fc1 is low when the capacitance CL is large, the phase margin pm is, for example, greater than or equal to 45 degrees and thus sufficient. However, when the capacitance CL is small, the increase in the frequency fc1 raises the gain. Thus, the phase margin pm becomes small and insufficient.
Therefore, in the series regulator circuit 50 shown in FIG. 5, the current consumption can be reduced. However, if the phase margin pm is insufficient when the capacitance CL of the load Lo changes, feedback control may not be performed stably. Thus, the load Lo connected to the voltage VOUT is restricted in terms of capacitance CL to stabilize the output of the series regulator circuit 50.